This invention relates to fractional frequency division for use in clock generators and, more particularly, to such clock generators for use in sampled data communication systems such as those employing oversampled analog-to-digital (A/D) and digital-to-analog (D/A) converters.
A modern communication system, such as a synchronous digital receiver or an oversampled A/D or D/A converter, typically requires the generation of different clock frequencies, the least common multiple (LCM) of which may be too high a frequency to generate practically. As a result, a high frequency reference, less than the LCM, is chosen such that fractional division may be used in order to generate some of the desired frequencies for the system. However, fractional division results in objectionable timing jitter in many instances.
An alternative to fractional division is to use multiple independent reference frequencies. This requires a phase locked loop (PLL) to synchronize the various frequencies in the system together. Clock jitter generally is present in a PLL, but at a much lower level than in a fractional divider. The penalty of such a scheme is additional cost and complexity. Various attempts have been made to generate fractionally divided clocks in a manner which reduces the jitter for a given set of divisors. One example is given in N. J. Malloy in U.S. Pat. No. 5,052,031 issued on Sep. 24, 1991. The output clock FOUT of the PLL is not an integral multiple of the reference clock FTB and typically has jitter, a fundamental by-product of the clock division process. More specifically, FOUT is generated in the Malloy patent by dividing FTB in each time interval by one of two integral divisors which are alternated in a predetermined sequence. The alternating of the divisors is done "as often as possible and in as uniform a manner as possible" so as to alleviate the adverse effects of jitter. Beyond these general guidelines, however, no specific criteria are provided for determining the optimum sequence of divisors for reducing the effects of jitter. Rather, the sole example for generating a 1.544 MHz output clock FOUT from a 51.84 MHz reference clock FTB entails an empirically determined sequence of dividing FTB by two divisors (33 and 34) over 193 time intervals.
Thus, there remains a need in the prior art for a deterministic technique for generating a sequence of divisors which alleviates the adverse effects of jitter for a given pair of divisors and for a given output clock frequency which is a non-integral multiple of an input clock frequency.